400G per Lane MSA Announces Project Progress and Future Outlook for Single-Lane 400G Active Electrical Cable Technical Specification Targeted at 3.2T Ethernet

[Shenzhen, China, September 10, 2026] During the 27th China International Optoelectronic Philosophical Exhibition (CIOE 2026), the Network Innovation and Development Alliance (NIDA) successfully hosted the "400G per Lane MSA Deliverables Release and High-Speed Optoelectronic Interconnect Technology Seminar." The NIDA 400G per Lane MSA, spearheaded jointly by China Mobile Communications Group Co., Ltd. and Huawei Technologies Co., Ltd., officially released the initial version of the first single-lane 400G Active Electrical Cable (AEC) technical specification.

Relying on NIDA, the 400G per Lane MSA was initiated and established in September 2025. Currently, it boasts over 30 members, encompassing nearly end-to-end industry chain participants including research institutes, operators, cloud service providers, equipment vendors, as well as chip, instrument, and meter manufacturers. Following the global release of the Single-Lane 400G Ethernet Physical Layer Whitepaper in April this year, this CIOE event marks another major milestone announcement by the 400G per Lane MSA, solidifying the foundational technology for 3.2T Ethernet in next-generation AI computing centers. High-speed 3.2Tbps Ethernet technology will undoubtedly become the primary technology for both intra-center and inter-center interconnectivity in future AI computing centers. NIDA's underlying Data Center Working Group, Network Evolution Working Group, Campus Network Working Group, Autonomous Network Working Group, and Cybersecurity Working Group cover virtually all horizontal network components. While refining its own technical endeavors, the 400G per Lane MSA will collaborate with other working groups to drive the end-to-end implementation of standards and specifications across network construction, maintenance, and optimization!

The publicly released Single-Lane 400G Active Electrical Cable (AEC) Technical Specification was primarily drafted by experts from member units including China Mobile and Huawei. It systematically defines the overall architecture and a complete set of electrical parameters for active electrical cables tailored for 400G per Lane signal transmission, fully supporting Ethernet transmission from 400GE to 1.6TE and future 3.2TE, providing the industry with a feasible option for single-lane 400G AEC interconnect technical specifications. Regarding software and hardware architecture, the specification defines the functional composition and working modes of active electrical cables, supporting combinations of multiple Forward Error Correction (FEC) coding techniques to adapt to different application scenarios. In terms of electrical parameters, the specification establishes a comprehensive set of performance metrics covering the transmitter, receiver, and full-link channel, while groundbreakingly defining three cable insertion loss tiers based on DSP performance and capabilities, fully accommodating varying transmission distance requirements from 1 meter to 2 meters and beyond 2 meters. Adopting mature industry measurement and testing methodologies wherever possible, the specification defines compliance test points and criteria at both host and module ends, ensuring interoperability among products from different vendors, making "testable and interoperable" an inherent, rigid requirement right from the inception of the standard. This specification provides chip, cable, and module manufacturers with a complete technical solution and unified R&D targets to directly guide their product development, boosting the global growth of the high-speed Ethernet interconnect industry for AI computing centers.

Single-lane 400G technology serves as the physical layer cornerstone for 3.2T Ethernet. As AI large model parameters surpass tens of trillions, demand for high-speed interconnects among GPUs in AI computing centers is growing rapidly, driving Ethernet port speeds toward 3.2T. The interface rate foundation relies on SerDes single-lane speeds: current 800G Ethernet is combined from eight 100G SerDes lanes, 1.6T Ethernet from eight 200G SerDes lanes, and future 3.2T Ethernet will be combined from eight 400G SerDes lanes. Crucially, although upper-layer technical approaches differ across AI computing center interconnect organizations such as InfiniBand, UALink, UEC, and UB, their foundation all relies on high-speed SerDes. Elevating the SerDes single-lane rate from 200G to 400G yields immense practical value for these various interconnect technologies.

To aggregate contributions from all end-to-end industry chain parties and jointly advance 400G per Lane technology toward maturity and ecosystem synergy, the 400G per Lane MSA held the High-Speed Optoelectronic Interconnect Technology Seminar alongside the project progress announcement. The seminar invited authoritative experts from domestic and international research and industrial institutions, operators, cloud service providers, equipment vendors, as well as chip and test instrument manufacturers—including China Mobile Research Institute, Huawei, CAICT, ZTE, Alibaba, Keysight Technologies, MultiLane, Jiyi Micro, and VIAVI Solutions—to engage in deep discussions regarding standards, technologies, testing, and industrial synergy for next-generation high-speed interconnects. Covering the entire industry chain from "Chip—Module—System—Test—Operation," the seminar represents a crucial step for 400G per Lane technology moving from specification text to engineering implementation, and from industry consensus to ecosystem synergy, which will greatly accelerate the industrial maturity and large-scale deployment of 400G per Lane technology.

The 400G per Lane MSA continuously attracts and gathers industry partners to promote the development of 400G per Lane Ethernet technology. Established under the NIDA framework in 2025, the MSA brings together over thirty leading enterprises in the high-speed interconnect field to jointly formulate 400G per Lane technical specifications and drive industry deployment. Advancing from a white paper to technical specifications, and further to full-industry-chain technical seminars, the 400G per Lane MSA is steadily propelling this technology from concept to realization, and from standards to ecosystem formation. Moving forward, the 400G per Lane MSA will continuously refine technical specifications, promote interoperability testing and verification among related manufacturers, and foster an open, collaborative ultra-high-speed Ethernet interconnect ecosystem, building a high-speed interconnect foundation for next-generation AI computing centers and accelerating the high-quality development of AI computing center infrastructure.